PHYSICAL DESIGN

Physical design 

• It is a process of transforming the circuit level description into the physical layout.
• In this layout, the position of the cells and routes for the interconnections between the cells are described by geometric representation. This geometric representation is called the Integrated Circuit layout.

Synthesis: 

1. Translation of RTL (Register Transfer Level) to Gate Level Netlist for Targeted technology.
2. It mainly focuses on logical optimization
3. It assumes a square shape without any physical data with lesser density.
4. it assumes only macro placement, not power routing
5. the main advantage of the synthesis is the Best optimized Logic.
6. Synthesis with Physical Data
7. Floorplan: Die & Core area, Macro placement, Power Ground routing is given for accuracy and optimization.
8. It is accurate than synthesis as Floorplan input is also given to the synthesis team.
9. RTL database is given as input, after the floor plan stage in the form of DEF file.

PD ASIC Flow

1. It starts from DataBase preparation (Inputs), this is from vendor libraries.
2. This DataBase is given as an input to the Synthesis team.
3. The synthesis team requires IP libraries with DataBase.
4. After Physical Synthesis PnR (Placement and Routing ) will be done.
5. After the routing stage RC Extraction by the EDA database in form of SPEF file.
6. The next stage is the Static Timing Analysis (STA).
7. The final stage is the GDSII output file.
8. Physical verification  like DRC, LVS..etc
9. Tape out in the Final Stage.

Common Questions:

1. Why DFF is used in Designs?---Race around condition is avoided in DFF.
2. What is meant by Banking?---Merging of Standard cells into one Standard cell of the same functionality. Pros: To save power and area. but it may cause congestion
3. Debanking?-- Splitting of  Banked Standard cell into many of the same functionality.