FILES

Types of Files

1. .V / .vhd (RTL or Gate Level Netlist or VHDL )
2. .lib --( Library file)--Liberty Timing File
3. .db --Timing information--some library files are in .db format.
4. .lef --(Layout Exchange Format)
5. .tf  --(Technology File)
6. .mw --(milky way )
7. .def --(Design Exchange Format)
8. .sdc --(Synopsys / Standard Design Constraints)
9. .tlu --(TLU+ Library)--Models help to compute R & C.
10. .itf --(Instance Toggling File)
11. upf --(Unified Power format)
12. .io --(input-output)
13. .map--mapping file
14. .spef --(Standard Parasitic Exchange Format)
15. .sdf --(Standard Delay Format)---used in synthesis.
16. .saif --(Switching Activity Interchange Format)
17. GDS--(Graphic Data Stream).
18. .tcl --(tool command language)

• .v /.vhd file consists of logical information (Verilog and VHDL file Representation)
• it is used as input to synthesis tool like Design Compiler or Genus..etc
• The netlist file obtained after synthesis is used as input to Floorplan.
• .vg file is used to differentiate gate-level netlist file

NETLIST:

It is the combination of sequential elements and their logical connectivity.

Netlist contains-

• Input and output information of the design.
• Wire information.
• Cell and instance information.
• Module information.
• Hierarchy information.
• Port information.

LIB file:

• .lib File (library file)/Liberty Timing file coded in ASCII  representation of timing power parameters for all the cells in the design for a particular technology node is described in this file
• .lib contains all the standard cell information like cell transition, cell delay, setup & hold time requirements, electrical and functional characteristics of a cell
• PVT conditions of the cells are also defined in the library.
• These are supplied by Vendors or Foundry.
• .db consists of Timing information

LEF(Library Exchange Format)--It has physical information about the design

Two types

• Technology lef
• Cell/macro lef

1.  Technology lef --It contains a metal layer and via information like

• Metal layer:
• Direction
• Pitch
• Width
• Area
• Spacing table
• Min enclosure area
• Diag spacing
• Diag min edge length
• Resistance
• Capacitance
• Thickness
• Antenna model and antenna area ratio
• DC current density

VIA information:

• Spacing
• Width
• Antenna model
• Antenna area ratio
• DC current Density

   2. Cell/Macro lef

• Class
• Origin
• Size
• Symmetry

    Pin:

• Antenna gate area
• Direction
• Usage
• Port

SDC (Synopsys design constraint)

•  Clock definition
• Create_clock
• Create_virtual clock
• Create generated clock
• Create clock uncertainty
• External delays
• Input delays
• Output delays
•  DRV’s
• Max transition, max capacitance, and max fanout
• Timing path exceptions
• False path
• Multi-cycle path
• Max delay
• Min delay  

• .mw / .FRAM consists of Frame view or Physical view--It consists of Physical Information.
• .cell view is the entire design view
• .sdc consists of Timing constraints
• .upf consists of power information
• .tlu+ helps to compute R & C values

• if .lib and .db files are changed entire standard cell information will be changed

Common questions

1. What is the input to the .lib file? -- Input transition & Output load.
2. What is the output to the .lib file?-- Output transition & cell delay.
3. Drive Strength? -- The Maximum capacitance load a device can drive. It is captured in the Library file as max_capacitance.
4. Fanout ?-- The number of gates it can drive