FLOORPLAN

Floor plan plays a critical role in the designing of a chip, Floorplan must be given utmost importance in designing a chip.
In Floor plan stage we will estimate

1. Die Area
2. Core Area
3. Utilization Ratio
4. The shape of the block
5. Creating Multiple Voltage domains & Gaurd bands in Multi-Voltage designs.
6. Flipping of First Site row if required.

In Floorplanning the cells are added for yield like

1. IO Buffers
2. Endcap cells
3. Decap cells
4. Tap cells  
5. Tie cells are added during the optimization of power planning

Pin Placement:

Before starting with macro placement first, you should finalize the pin placement.
The  following points should be considered at the time of pin placement:

1. Width and pitch of the pins should match with other blocks that are interfacing with your block.
2. Make sure your block pins are on routing tracks.
3. Make sure you leave 2 routing tracks on both the sides of the clock pins and pins which have NDR (Non-Default Rules) on their nets.
4. Place clock pins on higher layers.
5. Make sure none of the pins are overlapping.
6. Place IO buffers along with the pins if required.

Channel  Estimation:

At Block Level: 

The basic macro channel calculation formula is the following:

• channel = (no. of pins to be routed / no. of layers available) x layer pitch

Apart from the above equation, we should consider the following additional points while estimating macro channels.

1.      Channel should have at least one power and ground strap to power the cells within the channel.

2.      NDR routes (Clock routes, Isolation controls, Power switch controls) in the channel have to be budgeted for additional space requirements.

3.      Buffer count estimation in the channel for long route buffering and hold fixing.

While Considering at Full Chip Level:

·         The routing channel width is not just based on the two partitions but on all the signals that pass through or can pass through (if this is the shortest route) across the full chip and all the partitions.

·         Based on the floorplan and the data flow, a thorough estimate of the number of signals that can pass through the channel needs to be done

·         Out of these signals, an estimate on the approximate number of critical signals also need to be done. (if no data on this, we can have a pessimistic estimate of 30%).

• Assuming additional spacing for the critical nets, the total channel width is estimated based on the number of signals * (width + (2)*spacing). 
• Considering double spacing for the critical nets.
• Considering the horizontal or vertical channels, the corresponding metals need to be used for the estimation.
• For each of these metals, we need to estimate how many tracks per width are used for power routing and hence estimate the width required for the signal routing. Additional 20-30% width needs to be provided as a buffer

Macro Placement GuideLines--01:

1. Identify macros that are in the same hierarchy.
2. Place the macros by taking a look at the sharing of inputs/outputs across them. Eg: Generally memories are cascaded to get more storage. To increase no of bits, memories are cascaded horizontally i.e. memories share the same address bits and to increase no of locations memories are cascaded vertically i.e. memories share the same data bits. Based on these you should stack the memories horizontally/vertically.
3. Place the macro pins facing the core if the connectivity to the standard cells is higher.
4. Group the Macros based on MBIST modules.
5. Stack the macros based on routing blockages of the macros.
6. If the technology is 14nm or below, take particular care of macro spacing. If you are abutting them typically there are no issues seen, but if you are providing space between them, make sure you are not having any Base related DRCs, mainly on the RX layer.

Macro Placement GuideLines--02:

1. Place the Macros around the boundaries of the block by checking the connection to IO pins.
2. Avoid placing Macros at the center of the block, If placed it causes IR Drop at the center.
3. Estimate the channel between macros and place accordingly.
4. Check the orientation of Macros and align them.
5. Pins of the Macros should face the core area, it ensures the non-overlapping connectivity of the standard cells.
6. Avoid Notches in Macro placement.
7. Estimate the Hotspots and apply blockages if required.
8. Place Decap cells around the Macros.
9. Avoid Cris-Cross connections.
10. Keep out Margin or Cell Padding for Macros with more number of pins.