Congestion is a scenario in which the number of routable nets in a particular region of the design is higher than the resources available in that region. This could be because of the following reasons:
- Higher standard cell utilization in certain pockets of the design
- Clustering of Higher pin-count cells
- Wrong module placement resulting in the crisscrossing of routes.
- Higher routes in certain regions of the design
- Limited Metal stack used in the design
Ways to avoid congestion
- Don’t allow flops to be placed in channels. Flops in channels can result in huge congestion inside the channels. In the case of timing criticality, flops can be placed within channels with percentage blockages to restrict the usage of the channel.
- Visually check the macro channels after routing. You might not be seeing any congestion at placement and at routing, but you should check these channels visually and keep the margin for future routes.
- Always keep a tab on cell and route congestion. Maintain fewer bins with overflow.
- You can also provide max density constraints for placement; you can make it tighter for better congestion optimization.
- Make sure to check the placement of the cells which are small in size and having more pins like AOI/OAI cells. Try to give padding for these cells for better congestion/hold buffering.
- Make sure to check the placement of the sequential cells. Have sufficient gaps for these cells for hold buffering. Try to give padding for the sequential cells also for hold buffering.
- If you see cells clustered in certain pockets of the design, then try to spread them by creating small placement blockages in checkerboard fashion or some other fashion in that region.
- In deep sub-micron technologies, lower layers are manufactured in multiple masks. In these technologies fixing DP violations become challenging. To prevent these loop violations in the early stage by controlling the utilization of the lower layers. For ex use 60% of M2/M3 layers for routing.
