What is IR Drop?
IR drop is the voltage drop in the metal wires constituting the power grid before it reaches the power pins of the standard cells. It becomes very important to limit the IR drop as it affects the speed of the cells and the overall performance of the chip. There are two types of IR drops:
1. Static
2. Dynamic
Static IR Drop: Static IR drop is an average voltage drop for the design. It is dependent on the RC of the power grid connecting the power supply to the respective standard cells. The average current depends totally on the time period. Gate-channel leakage current is the major reason for the static IR drop.
Vstatic_drop = Iavg x Rwire [Iavg are all factors of leakage currents ]
Dynamic IR Drop: Dynamic IR drop is a drop in the voltage due to the high switching activity of transistors. It happens when there is an increasing demand for current from the power supply due to switching activities of the chip. Dynamic IR drop depends on the switching time of the logic and is less dependent on the clock period. Dynamic IR drop evaluates the IR drop caused when a large number of circuitry switches at the same time, causing peak current demand. This current demand could be highly localized and could be brief within a single clock cycle (a few hundred ps), and could result in an IR drop that causes additional setup or hold-time violations. Typically, high IR drop impact on clock networks causes hold-time violations, while IR drop on data path signal nets causes setup-time violations. In such cases, you can separate the standard cells apart so that the burden on a given bump to feed many standard cells, which have high switching activity, can be mitigated.
Vdynamic_drop = L (di/dt) [current L is due to switching current]
1. Static
2. Dynamic
Static IR Drop: Static IR drop is an average voltage drop for the design. It is dependent on the RC of the power grid connecting the power supply to the respective standard cells. The average current depends totally on the time period. Gate-channel leakage current is the major reason for the static IR drop.
Vstatic_drop = Iavg x Rwire [Iavg are all factors of leakage currents ]
Dynamic IR Drop: Dynamic IR drop is a drop in the voltage due to the high switching activity of transistors. It happens when there is an increasing demand for current from the power supply due to switching activities of the chip. Dynamic IR drop depends on the switching time of the logic and is less dependent on the clock period. Dynamic IR drop evaluates the IR drop caused when a large number of circuitry switches at the same time, causing peak current demand. This current demand could be highly localized and could be brief within a single clock cycle (a few hundred ps), and could result in an IR drop that causes additional setup or hold-time violations. Typically, high IR drop impact on clock networks causes hold-time violations, while IR drop on data path signal nets causes setup-time violations. In such cases, you can separate the standard cells apart so that the burden on a given bump to feed many standard cells, which have high switching activity, can be mitigated.
Vdynamic_drop = L (di/dt) [current L is due to switching current]
Electromigration Mitigation
1. Apply NDR (Non-default Rule) on the violated nets (vulnerable nets)
1. Apply NDR (Non-default Rule) on the violated nets (vulnerable nets)
- Once you have the EM results, you can take the net shapes and re-route those nets with the NDR. Applying NDR involves routing of clock nets using double-wide or triple-wide metal with more spacing. This will quickly remove most of the violations and can even predict the nets, which are more likely to have EM violations based on two parameters: 1) driver strength and 2) load
- You can filter out nets with more load and heavy drivers and move them to NDR.
- You can decide the threshold load for different driving strength based on project statistics.
2. Restricting load target for nets
- Restricting or reducing the load on the nets can also be helpful in preventing the occurrence of electromigration. For example, we saw 142fF as an average capacitance in the design. Based on the statistics of a few experiments, we restricted all nets to have a maximum 60fF of load. As a result, we saw a very good improvement in signal EM as well as on average net length.
IR Drop Mitigation
1. Padding clock cells: when it comes to IR drop issues, clock structure is the primary culprit for the power consumption of the chip due to high clock switching. However, with padding clock cell technique, clock buffers/inverters, and clock gate cells are given extra areas as keepout regions to avoid placement of standard cells and any excessive cell density around them. This helps to prevent the dynamic IR drop.
2 . Cell Padding/Decap insertion around cells within a dynamic IR hotspot region
1. Padding clock cells: when it comes to IR drop issues, clock structure is the primary culprit for the power consumption of the chip due to high clock switching. However, with padding clock cell technique, clock buffers/inverters, and clock gate cells are given extra areas as keepout regions to avoid placement of standard cells and any excessive cell density around them. This helps to prevent the dynamic IR drop.
2 . Cell Padding/Decap insertion around cells within a dynamic IR hotspot region
- Some cells with high driving strength create dynamic IR drop issues. You can give cell padding to these cells or insert decap cells around it or IR hotspot region to prevent IR drop issues.
