Synthesis-- Summary

 

Synthesis

Synthesis is the process of converting RTL i.e. synthesizable Verilog code to technology-specific gate-level netlist. Netlist basically includes nets, sequential and combinational cells, and their connectivity information.

Goals of Synthesis -

1. To get a gate-level netlist
2. Inserting clock gates
3. Logic optimization
4. Inserting DFT logic
5. Logic equivalence between RTL and netlist should be maintained

Inputs for Synthesis Tool -

1. .tf- technology-related information.
2. .lib-timing info of standard cell & macros
3. .v- RTL code.
4. SDC- Timing constraints.
5. UPF- power the intent of the design.
6. Scan config- Scan related info like scan chain length, scan IO, which flops are to be considered in the scan chains.

For Physical aware synthesis -

1. RC co-efficient file (tluplus).
2. LEF/FRAM- abstract view of the cell.
3. Floorplan DEF- locations of IO ports and macros.

Synthesis Flow -
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Analyze -
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This step do syntax checking on RTL (Verilog) code

Elaborate -
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First, all lower-level blocks brought into synthesis tool.
Verilog code and arithmetic operators are converted into Gtech and DW components. These are technology-independent libraries.

Gtech- contains basic logic gates &flops.
DesignWare- contains complex cells like FIFO, counters.

Analyses the design hierarchy.
Removes empty switches and dead branches.
Detects asynchronous reset.
Converts decision trees to mux.
Converts synchronous to Dlatch/DFF.

Do FSM Pass:
Detects FSM logic and extracts the no of input, output bits and state bits.
Converts FSM logic to basic logic.

Do Memory Pass:
Merging DFF to memory write(memwr) and memory read (memrd)
Consolidating memwr/memrd cells
Generate memory (mem) cells
Mapping mem cells to basic logic

Import timing and power constraints -
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Once the design is extracted in the form of technology-independent cells, timing constraints are imported from the SDC file.

If the design consists of multiple power domains, then using the UPF power domains, isolation cells, level shifters, power switches, retention flops are placed.

Clock gating -
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Due to the high switching activity of clock a lot of dynamic power is consumed. One of the techniques to lower the dynamic power is clock gating.
Clock gating is inserted in existing design for design power reduction.
(We will discuss clock gating in details in another topic)

Optimization -

1. Performs logic and design optimization.
2. Overall Optimization can be categorized as follows
3. Logic optimization & Design optimization.

Logic optimization:

1. Constant folding
2. Detect identical cells
3. Optimize mux (dead branches in mux)
4. Consolidate mux and reduce inputs (many to single)
5. Remove DFF with a constant value
6. Remove unused cells and wires

Design optimization:

1. Reduce TNS and WNS
2. Power Optimization
3. Area Optimization
4. Meet the timing DRV’s
5. Incremental clock gating

DFT insertion (Design for Testing) -

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DFT circuits are used for testing each and every a node in the design.
More the numbers of nodes that can be tested with some targeted pattern, more is the coverage. Scan chains are inserted in scan-based designs.
(We will discuss details scan-based design in later topic)

Incremental Compile -
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Technology mapping of DFT circuit
Optimization of the design

Outputs of Synthesis -
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1. Netlist
2. SDC file
3. UPF file
4. Scan Def

How to Qualify Synthesis Results?
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1. Synthesis results can be qualified based on the following points –
2. Check if the RTL and netlist are logically equivalent (LEC/FM).
3. Check if SDC and UPF are generated after synthesis and also check their completeness.
4. Check if there are any assign statements.
5. Combinational loops
6. Un-clocked registers
7. unconstrained IO’s
8. IO delay missing
9. Un-expandable clocks
10. Master-slave separation
11. multiple clocks
12. Checks related to design
13. Floating pins
14. multi driven inputs
15. un-driven inputs
16. un-driven outputs
17. normal cells in the clock path
18. pin direction mismatch
19. Check for don’t use cells