CTS

  CTS Pre requisites

1. Placement database should be legal

2. Timing/ Congestion is Good

3. Remove Ideal Network

4. Remove Don’t use and Don’t touch on CTS Buffers and Inverters

5. Remove Fixed attribute on Clock Cells

6. Remove  Existing Buffer tree -- In high fanout it may add buffers

7. CTS Exception

CTS Constraints

1. Clock Tranistions 

2. Clock Capacitance 

3. Clock Fanout 

4. Latency

5. Skew

CTS Setup

1. CTS Buffers

2. NDR rules -2W -2S or 1W 3S

3. Clock Metal layers 

4. Clock Algorithms

5. Clock Balance points

CLOCK_OPT

Reports

1. Report_Clock_qor

2. Report_clock_tree –summary –latency –skew –DRV

3. Report_ Clock_tree Exceptions

After CTS

1. Clock tree is correctly built or not.

2. Enable hold optimizations.

3. Don’t use cts buffers.

4. Enable hold cells.

5. Start optimization.

Special Cells placement in power gated implementations like AON / LS / ISO / RET cells

 These cells (AON/LS/ISO/RET) are present in multi-power domain based designs.

1. LS/ISO cells are to be placed at the power domain crossings.
2. Placement of these cells can be done by the tool provided the secondary power routes are drawn at regular intervals through-out the design.
3. Bounds/Inst Groups for these cells are created in case of non availability of secondary power routes through-out the design.
4. AON cells are needed if the Always-On signal goes through the switchable region. If your design is congested and if you don’t want to pass these signals through the core logic then you can do the following:
   • Create bounds for these cells around the edge of the switchable region for every x microns, here x is the max length that one AON cell can drive. This is if you don’t want these signals not to go through the core.
   • Create islands for the AON power inside the switchable domain for every x microns, here x is the max length one buffer cell can drive. This is if you have congestion and area concerns.
5.  Finalize the RET cells placement after one placement trail, this is if you are creating a bound for these cells.

PHYSICAL DESIGN

 Physical design 

• It is a process of transforming the circuit level description into the physical layout.
• In this layout, the position of the cells and routes for the interconnections between the cells are described by geometric representation. This geometric representation is called the Integrated Circuit layout.

Synthesis: 

1. Translation of RTL (Register Transfer Level) to Gate Level Netlist for Targeted technology.
2. It mainly focuses on logical optimization
3. It assumes a square shape without any physical data with lesser density.
4. it assumes only macro placement, not power routing
5. the main advantage of the synthesis is the Best optimized Logic.
6. Synthesis with Physical Data
7. Floorplan: Die & Core area, Macro placement, Power Ground routing is given for accuracy and optimization.
8. It is accurate than synthesis as Floorplan input is also given to the synthesis team.
9. RTL database is given as input, after the floor plan stage in the form of DEF file.

PD ASIC Flow

1. It starts from DataBase preparation (Inputs), this is from vendor libraries.
2. This DataBase is given as an input to the Synthesis team.
3. The synthesis team requires IP libraries with DataBase.
4. After Physical Synthesis PnR (Placement and Routing ) will be done.
5. After the routing stage RC Extraction by the EDA database in form of SPEF file.
6. The next stage is the Static Timing Analysis (STA).
7. The final stage is the GDSII output file.
8. Physical verification  like DRC, LVS..etc
9. Tape out in the Final Stage.

Common Questions:

1. Why DFF is used in Designs?---Race around condition is avoided in DFF.
2. What is meant by Banking?---Merging of Standard cells into one Standard cell of the same functionality. Pros: To save power and area. but it may cause congestion
3. Debanking?-- Splitting of  Banked Standard cell into many of the same functionality.

Input Files for Physical Design

 Types of Files

1. .V / .vhd (RTL or Gate Level Netlist or VHDL )
2. .lib --( Library file)--Liberty Timing File
3. .db --Timing information--some library files are in .db format.
4. .lef --(Layout Exchange Format)
5. .tf  --(Technology File)
6. .mw --(milky way )
7. .def --(Design Exchange Format)
8. .sdc --(Synopsys / Standard Design Constraints)
9. .tlu --(TLU+ Library)--Models help to compute R & C.
10. .itf --(Instance Toggling File)
11. upf --(Unified Power format)
12. .io --(input-output)
13. .map--mapping file
14. .spef --(Standard Parasitic Exchange Format)
15. .sdf --(Standard Delay Format)---used in synthesis.
16. .saif --(Switching Activity Interchange Format)
17. GDS--(Graphic Data Stream).
18. .tcl --(tool command language)

• .v /.vhd file consists of logical information (Verilog and VHDL file Representation)
• it is used as input to synthesis tool like Design Compiler or Genus..etc
• The netlist file obtained after synthesis is used as input to Floorplan.
• .vg file is used to differentiate gate-level netlist file

NETLIST:

It is the combination of sequential elements and their logical connectivity.

Netlist contains-

• Input and output information of the design.
• Wire information.
• Cell and instance information.
• Module information.
• Hierarchy information.
• Port information.

LIB file:

• .lib File (library file)/Liberty Timing file coded in ASCII  representation of timing power parameters for all the cells in the design for a particular technology node is described in this file
• .lib contains all the standard cell information like cell transition, cell delay, setup & hold time requirements, electrical and functional characteristics of a cell
• PVT conditions of the cells are also defined in the library.
• These are supplied by Vendors or Foundry.
• .db consists of Timing information

LEF(Library Exchange Format)--It has physical information about the design

Two types

• Technology lef
• Cell/macro lef

1.  Technology lef --It contains a metal layer and via information like

• Metal layer:
• Direction
• Pitch
• Width
• Area
• Spacing table
• Min enclosure area
• Diag spacing
• Diag min edge length
• Resistance
• Capacitance
• Thickness
• Antenna model and antenna area ratio
• DC current density

VIA information:

• Spacing
• Width
• Antenna model
• Antenna area ratio
• DC current Density

   2. Cell/Macro lef

• Class
• Origin
• Size
• Symmetry

    Pin:

• Antenna gate area
• Direction
• Usage
• Port

SDC (Synopsys design constraint)

•  Clock definition
• Create_clock
• Create_virtual clock
• Create generated clock
• Create clock uncertainty
• External delays
• Input delays
• Output delays
•  DRV’s
• Max transition, max capacitance, and max fanout
• Timing path exceptions
• False path
• Multi-cycle path
• Max delay
• Min delay  

• .mw / .FRAM consists of Frame view or Physical view--It consists of Physical Information.
• .cell view is the entire design view
• .sdc consists of Timing constraints
• .upf consists of power information
• .tlu+ helps to compute R & C values

• if .lib and .db files are changed entire standard cell information will be changed

Common questions

1. What is the input to the .lib file? -- Input transition & Output load.
2. What is the output to the .lib file?-- Output transition & cell delay.
3. Drive Strength? -- The Maximum capacitance load a device can drive. It is captured in the Library file as max_capacitance.
4. Fanout ?-- The number of gates it can drive 

FLOORPLAN

 Floor plan plays a critical role in the designing of a chip, Floorplan must be given utmost importance in designing a chip.

In Floor plan stage we will estimate

1. Die Area
2. Core Area
3. Utilization Ratio
4. The shape of the block
5. Creating Multiple Voltage domains & Gaurd bands in Multi-Voltage designs.
6. Flipping of First Site row if required.

In Floorplanning the cells are added for yield like

1. IO Buffers
2. Endcap cells
3. Decap cells
4. Tap cells  
5. Tie cells are added during the optimization of power planning

Pin Placement:

Before starting with macro placement first, you should finalize the pin placement.
The  following points should be considered at the time of pin placement:

1. Width and pitch of the pins should match with other blocks that are interfacing with your block.
2. Make sure your block pins are on routing tracks.
3. Make sure you leave 2 routing tracks on both the sides of the clock pins and pins which have NDR (Non-Default Rules) on their nets.
4. Place clock pins on higher layers.
5. Make sure none of the pins are overlapping.
6. Place IO buffers along with the pins if required.

Channel  Estimation:

At Block Level: 

The basic macro channel calculation formula is the following:

• channel = (no. of pins to be routed / no. of layers available) x layer pitch

Apart from the above equation, we should consider the following additional points while estimating macro channels.

1.      Channel should have at least one power and ground strap to power the cells within the channel.

2.      NDR routes (Clock routes, Isolation controls, Power switch controls) in the channel have to be budgeted for additional space requirements.

3.      Buffer count estimation in the channel for long route buffering and hold fixing.

While Considering at Full Chip Level:

 The routing channel width is not just based on the two partitions but on all the signals that pass through or can pass through (if this is the shortest route) across the full chip and all the partitions.

Based on the floorplan and the data flow, a thorough estimate of the number of signals that can pass through the channel needs to be done

Out of these signals, an estimate on the approximate number of critical signals also need to be done. (if no data on this, we can have a pessimistic estimate of 30%).

• Assuming additional spacing for the critical nets, the total channel width is estimated based on the number of signals * (width + (2)*spacing). 
• Considering double spacing for the critical nets.
• Considering the horizontal or vertical channels, the corresponding metals need to be used for the estimation.
• For each of these metals, we need to estimate how many tracks per width are used for power routing and hence estimate the width required for the signal routing. Additional 20-30% width needs to be provided as a buffer

Macro Placement GuideLines--01:

1. Identify macros that are in the same hierarchy.
2. Place the macros by taking a look at the sharing of inputs/outputs across them. Eg: Generally memories are cascaded to get more storage. To increase no of bits, memories are cascaded horizontally i.e. memories share the same address bits and to increase no of locations memories are cascaded vertically i.e. memories share the same data bits. Based on these you should stack the memories horizontally/vertically.
3. Place the macro pins facing the core if the connectivity to the standard cells is higher.
4. Group the Macros based on MBIST modules.
5. Stack the macros based on routing blockages of the macros.
6. If the technology is 14nm or below, take particular care of macro spacing. If you are abutting them typically there are no issues seen, but if you are providing space between them, make sure you are not having any Base related DRCs, mainly on the RX layer.

Macro Placement GuideLines--02:

1. Place the Macros around the boundaries of the block by checking the connection to IO pins.
2. Avoid placing Macros at the center of the block, If placed it causes IR Drop at the center.
3. Estimate the channel between macros and place accordingly.
4. Check the orientation of Macros and align them.
5. Pins of the Macros should face the core area, it ensures the non-overlapping connectivity of the standard cells.
6. Avoid Notches in Macro placement.
7. Estimate the Hotspots and apply blockages if required.
8. Place Decap cells around the Macros.
9. Avoid Criss-Cross connections.
10. Keep out Margin or Cell Padding for Macros with more number of pins.

Synthesis-- Summary

 

Synthesis

Synthesis is the process of converting RTL i.e. synthesizable Verilog code to technology-specific gate-level netlist. Netlist basically includes nets, sequential and combinational cells, and their connectivity information.

Goals of Synthesis -

1. To get a gate-level netlist
2. Inserting clock gates
3. Logic optimization
4. Inserting DFT logic
5. Logic equivalence between RTL and netlist should be maintained

Inputs for Synthesis Tool -

1. .tf- technology-related information.
2. .lib-timing info of standard cell & macros
3. .v- RTL code.
4. SDC- Timing constraints.
5. UPF- power the intent of the design.
6. Scan config- Scan related info like scan chain length, scan IO, which flops are to be considered in the scan chains.

For Physical aware synthesis -

1. RC co-efficient file (tluplus).
2. LEF/FRAM- abstract view of the cell.
3. Floorplan DEF- locations of IO ports and macros.

Synthesis Flow -
---------------------------

Analyze -
---------------
This step do syntax checking on RTL (Verilog) code

Elaborate -
-----------------
First, all lower-level blocks brought into synthesis tool.
Verilog code and arithmetic operators are converted into Gtech and DW components. These are technology-independent libraries.

Gtech- contains basic logic gates &flops.
DesignWare- contains complex cells like FIFO, counters.

Analyses the design hierarchy.
Removes empty switches and dead branches.
Detects asynchronous reset.
Converts decision trees to mux.
Converts synchronous to Dlatch/DFF.

Do FSM Pass:
Detects FSM logic and extracts the no of input, output bits and state bits.
Converts FSM logic to basic logic.

Do Memory Pass:
Merging DFF to memory write(memwr) and memory read (memrd)
Consolidating memwr/memrd cells
Generate memory (mem) cells
Mapping mem cells to basic logic

Import timing and power constraints -
--------------------------------------------------------------
Once the design is extracted in the form of technology-independent cells, timing constraints are imported from the SDC file.

If the design consists of multiple power domains, then using the UPF power domains, isolation cells, level shifters, power switches, retention flops are placed.

Clock gating -
----------------------
Due to the high switching activity of clock a lot of dynamic power is consumed. One of the techniques to lower the dynamic power is clock gating.
Clock gating is inserted in existing design for design power reduction.
(We will discuss clock gating in details in another topic)

Optimization -

1. Performs logic and design optimization.
2. Overall Optimization can be categorized as follows
3. Logic optimization & Design optimization.

Logic optimization:

1. Constant folding
2. Detect identical cells
3. Optimize mux (dead branches in mux)
4. Consolidate mux and reduce inputs (many to single)
5. Remove DFF with a constant value
6. Remove unused cells and wires

Design optimization:

1. Reduce TNS and WNS
2. Power Optimization
3. Area Optimization
4. Meet the timing DRV’s
5. Incremental clock gating

DFT insertion (Design for Testing) -

------------------------------------------------------
DFT circuits are used for testing each and every a node in the design.
More the numbers of nodes that can be tested with some targeted pattern, more is the coverage. Scan chains are inserted in scan-based designs.
(We will discuss details scan-based design in later topic)

Incremental Compile -
------------------------------------
Technology mapping of DFT circuit
Optimization of the design

Outputs of Synthesis -
------------------------------------

1. Netlist
2. SDC file
3. UPF file
4. Scan Def

How to Qualify Synthesis Results?
--------------------------------------------------------------

1. Synthesis results can be qualified based on the following points –
2. Check if the RTL and netlist are logically equivalent (LEC/FM).
3. Check if SDC and UPF are generated after synthesis and also check their completeness.
4. Check if there are any assign statements.
5. Combinational loops
6. Un-clocked registers
7. unconstrained IO’s
8. IO delay missing
9. Un-expandable clocks
10. Master-slave separation
11. multiple clocks
12. Checks related to design
13. Floating pins
14. multi driven inputs
15. un-driven inputs
16. un-driven outputs
17. normal cells in the clock path
18. pin direction mismatch
19. Check for don’t use cells

Electron Migration ( EM )

 Electromigration (EM) is the movement of material that results from the transfer of momentum between electrons and metal atoms under the influence of an applied electric field. This momentum transfer causes the metal atoms to be displaced from their original positions. 

This effect increases with increasing current density in a wire, and at higher temperatures the momentum transfer becomes more severe. Thus in sub-100nm designs, with higher device currents, narrower wires, and increasing on-die temperatures, the reliability of interconnects and their possible degradation from EM is a serious concern. 

The transfer of metal ions over time from EM can lead to either narrowing or hillocks (bumps) in the wires. 

Narrowing of the wire can result in degradation of performance, or in extreme cases can result in the complete opening of the conduction path as shown in the picture below.

Widening and bumps in the wire can result in shorts to neighboring wires, especially if they are routed at the minimum pitch in the newer technologies. Foundries typically specify the maximum amount of pitch in the newer technologies.

Broadly EM is classified as cell EM and Wire EM.

Cell EM

Cell EM rules address the EM caused by current within a cell. Cell EM rules operate on the principle that, although the currents within a cell cannot be calculated due to a lack of physical layout information, they can be controlled based on external physical entities. The tool estimates the detrimental effects of currents within a cell as a function of its, 

1. Output load
2. Input slew
3. Switching frequency

Wire EM 
There are two types of wire EM:

Signal EM –  It is performed net by net, simulating the charging and discharging for all possible paths to determine the worst-case average and RMS current for each wire segment. Once currents are determined, the current density is computed.

Self-Heating: It is a physical design issue that takes place in the output nodes/interconnects of circuits that charge and discharge frequently, Leads to other problems caused by heating, like an increase in resistance of the interconnect and hence an increase in charging time of the node. Also, it causes thermal reliability issues.

Techniques to solve EM:

• Increasing the metal width to reduce the current density is a typical solution
• For a via EM violation, you can increase the number of vias to fix potential EM issues
• Additional straps for the current supply
• Layer switching is another option; typically, upper metal layers in the technology have higher current
• driving capability (due to greater thickness)
• Reduce the cell size driving the signal net if we have positive slack on that path 
•