IR DROP

 What is IR Drop?

IR drop is the voltage drop in the metal wires constituting the power grid before it reaches the power pins of the standard cells. It becomes very important to limit the IR drop as it affects the speed of the cells and the overall performance of the chip. There are two types of IR drops:

1.      Static
2.      Dynamic

Static IR Drop:  Static IR drop is an average voltage drop for the design. It is dependent on the RC of the power grid connecting the power supply to the respective standard cells. The average current depends totally on the time period. Gate-channel leakage current is the major reason for the static IR drop.

Vstatic_drop = Iavg  x Rwire  [Iavg are all factors of leakage currents ]  

Dynamic IR Drop:  Dynamic IR drop is a drop in the voltage due to the high switching activity of transistors. It happens when there is an increasing demand for current from the power supply due to switching activities of the chip. Dynamic IR drop depends on the switching time of the logic and is less dependent on the clock period. Dynamic IR drop evaluates the IR drop caused when a large number of circuitry switches at the same time, causing peak current demand.  This current demand could be highly localized and could be brief within a single clock cycle (a few hundred ps), and could result in an IR drop that causes additional setup or hold-time violations. Typically, high IR drop impact on clock networks causes hold-time violations, while IR drop on data path signal nets causes setup-time violations. In such cases, you can separate the standard cells apart so that the burden on a given bump to feed many standard cells, which have high switching activity, can be mitigated.

Vdynamic_drop = L (di/dt) [current L is due to switching current]

Electromigration Mitigation 

1.      Apply NDR (Non-default Rule) on the violated nets (vulnerable nets)

• Once you have the EM results, you can take the net shapes and re-route those nets with the NDR. Applying NDR involves routing of clock nets using double-wide or triple-wide metal with more spacing. This will quickly remove most of the violations and can even predict the nets, which are more likely to have EM violations based on two parameters: 1) driver strength and 2) load

• You can filter out nets with more load and heavy drivers and move them to NDR. 

• You can decide the threshold load for different driving strength based on project statistics.

  2.   Restricting load target for nets

• Restricting or reducing the load on the nets can also be helpful in preventing the occurrence of electromigration. For example, we saw 142fF as an average capacitance in the design. Based on the statistics of a few experiments, we restricted all nets to have a maximum 60fF of load. As a result, we saw a very good improvement in signal EM as well as on average net length.

IR Drop Mitigation 

1.      Padding clock cells: when it comes to IR drop issues, clock structure is the primary culprit for the power consumption of the chip due to high clock switching. However, with padding clock cell technique, clock buffers/inverters, and clock gate cells are given extra areas as keepout regions to avoid placement of standard cells and any excessive cell density around them. This helps to prevent the dynamic IR drop.

2  . Cell Padding/Decap insertion around cells within a dynamic IR hotspot region

• Some cells with high driving strength create dynamic IR drop issues. You can give cell padding to these cells or insert decap cells around it or IR hotspot region to prevent IR drop issues.

GUIDELINES FOR PLACING ANALOG BLOCK AT FLOOR PLAN STAGE

 Analog blocks are quite sensitive to noise and below precautions need to be taken

• Sufficient isolation is to be provided for the Analog layout from the digital logic. This includes both the IO and core logic.

• Normally, the IO power for the Analog block needs to be isolated. Even if the power source is the same, it is important to isolate the power connections to the analog block IOs from the other IOs. 

• They need to be isolated at the package source. For very critical blocks, it is needed to isolate even the source and the ground completely. Providing an independent power source may not always be possible and need to be looked at from the architecture side.

• Providing an isolated ground can be even more difficult to implement at a system level. It is better to have a separate mesh/connection from the source of power/ground itself

• The power for the Analog IO interface and a block needs to be separately estimated and accordingly the number of power and ground IOs/bump pads need to be estimated. Since the Analog IOs are sensitive to noise, it is recommended to have a power/ground pad alternatively after each signal IO

• The ESD rail is generally common across all the IOs. However, in rare cases, there may be a need to have a separate ESD rail for the analog IO interface (for very critical and sensitive IOs).

• Even the analog block may have digital logic inside and only part of it may be true analog logic and custom layout. It helps to have this information so we can apply the isolation accordingly.

• There may be core voltage being used in the analog block but it may be for digital logic or analog logic within the block. If it is for analog logic, the supply to it needs to be isolated from the core mesh (used by the core digital logic). 

• One power source may be placed close to the analog block and from there, the power routed to the power pins of the block and not shared with other logic.  This power routing needs to be of sufficient width (based on the power requirement and the distance from the source) and with 3-4 additional spacing.

• The analog logic area of the block needs to be isolated from the digital logic placement area. The isolation area can be filled with decaps. For an extended width from the isolation, care to be taken to not use high drive cells

• All the power pins of the block are to be connected with the appropriate width and at least the width of the power pin

Congestion and Techniques to avoid it !!!

 Congestion is a scenario in which the number of routable nets in a particular region of the design is higher than the resources available in that region. This could be because of the following reasons:

1. Higher standard cell utilization in certain pockets of the design
2. Clustering of Higher pin-count cells
3. Wrong module placement resulting in the crisscrossing of routes.
4. Higher routes in certain regions of the design
5. Limited Metal stack used in the design

Ways to avoid congestion

1. Don’t allow flops to be placed in channels. Flops in channels can result in huge congestion inside the channels. In the case of timing criticality, flops can be placed within channels with percentage blockages to restrict the usage of the channel.
2. Visually check the macro channels after routing. You might not be seeing any congestion at placement and at routing, but you should check these channels visually and keep the margin for future routes.
3. Always keep a tab on cell and route congestion. Maintain fewer bins with overflow.
4. You can also provide max density constraints for placement; you can make it tighter for better congestion optimization.
5. Make sure to check the placement of the cells which are small in size and having more pins like AOI/OAI cells. Try to give padding for these cells for better congestion/hold buffering.
6. Make sure to check the placement of the sequential cells. Have sufficient gaps for these cells for hold buffering. Try to give padding for the sequential cells also for hold buffering.
7. If you see cells clustered in certain pockets of the design, then try to spread them by creating small placement blockages in checkerboard fashion or some other fashion in that region.
8. In deep sub-micron technologies, lower layers are manufactured in multiple masks. In these technologies fixing DP violations become challenging. To prevent these loop violations in the early stage by controlling the utilization of the lower layers. For ex use 60% of M2/M3 layers for routing.

Redistribution Layer (RDL)

 Redistribution Layer (RDL)

The redistribution layer (RDL) is the interface between chip and package for flip-chip assembly (shown in fig below). An RDL is an extra metal layer consisting of wiring on top of core metals that makes the I/O pads of the die available for bonding out other locations such as bump pads. Bumps are usually placed in a grid pattern and each one is molded with two pads (one on the top and one on the bottom) that are then attached to the RDL and package substrate respectively

Engineers use a redistribution layer (RDL) in flip-chip designs to redistribute I/O pads to bump pads without changing the I/O pad placement. The RDL, therefore, serves as the layer connecting I/O pads and bump pads. However, traditional routing capacity may be insufficient to handle sizable designs, in which the RDL may be very congested and especially when there is a less-than-optimal I/O-bump assignment. As a result, routing may not be completed within a single layer even with manual routing.

As demand for more input/output (I/O) increases, traditional wire-bond packaging may not effectively support thousands of I/Os. Flip-chip assembly is commonly used in place of wire bond because it reduces chip area while supporting many more I/Os. It also greatly reduces inductance, allows high-speed signals, and possess better heat conductivity properties. The flip-chip ball grid array (FCBGA) is also growing in popularity as an alternative methodology for high I/O count chips.